1. Field of the Invention
The present invention relates generally to a packet switching system. More specifically, the invention relates to a packet switching technology in a digital communication network employing a packet.
2. Description of the Related Art
High attention has been attracted for a high speed packet switching system for transmitting and exchanging information at ultra-high speed by transforming all information, such as voice, data, image and so forth in packets and employing simplified protocol. In such high speed packet switching system, a large scale packet switching system for more than several hundreds of channels is realized by connecting middle or small scale packet switches in a plurality of stages.
In such case, there is a system, in which the first stage packet switch does not perform a path selection for the input packet and the input packet is uniformly supplied to subsequent stages of packet switch regardless of its address information and path selection is performed in the subsequent stages of packet switch for simplification of a path selection control
and for preventing an internal blocking (which means a condition wherein a call cannot be connected due to blocking of an internal link despite of presence of vacant capacity of incoming channel and outgoing channel).
In this system, since each of packets of the same call passes different paths and thus it causes different delay time of respective packets having passed different paths, the order of the packet in the same call has an irregular sequence. A solution for this problem has been disclosed in a paper entitled "A Study on Control Algorithm for Large Scale ATM Switch" in The Institute of Electronics, Information and Communication Engineers Technical Study Report, Switching System Engineering--SSE 89-173, 1989.
The conventional system will be discussed hereinafter with reference to FIG. 9. FIG. 9 shows the block diagram of the conventional system. In the above-identified literature, the switching system is constituted of three stages of switches, as shown in FIG. 9. Each of the input ports 7.sub.11 -7.sub.88 are provided for each of the first stage switches and each of the eight output ports 9.sub.11 -9.sub.88 are provided for each of the third stage switches.
Time stamping circuits 4.sub.11 -4.sub.88 are provided for each of the input ports and packet buffer circuit 5.sub.11 -5.sub.88 are also provided for each of the output ports. The time stamping circuit provides a time stamp representing input time information for each of the packets input at an input port. Each of input packets is distributed to respective second stage switches 2.sub.1 -2.sub.8 by the first stage switch regardless of address information, and then switched to desired destination per packet by the second stage switches 2.sub.1 -2.sub.8 and third stage switches 3.sub.1 -3.sub.8. After having passed through switches, the packets are once stored in packet sorting circuits 5.sub.11 -5.sub.88 which are provided at outlets of the third stage of switches 3.sub.1 -3.sub.8. Those stored packet are output to output ports 9.sub.11 -9.sub.88 in accordance with the time information order of a period longer than a predetermined period of time (a possible maximum delay period required for passing through the first stage switches 1.sub.1 -1.sub.8 to the third stage switches 3.sub.1 -3.sub.8) and whereby each of the packets of the same cell is arranged in order.
In such packet switching system, the delay period of the packet is inherently increased since the packet buffer circuits provide delay the packet for a period longer than the predetermined period of time. In addition, it is inherently required to make judgement whether the delay period exceeds the predetermined period of time for respective packets for large amount of control which results in complicated hardware construction.